This document is part of Altera HardCopy IV Device Handbook Volume 1 and introduces the features and characteristics of the HardCopy IV device family.
This document provides an overview of the Altera HardCopy IV device family, which consists of 40-nm system-capable ASICs designed with an FPGA design flow. The family is supported by Quartus II software and Stratix IV FPGAs to enable in-system prototyping and reduce design risk.
| Process Node | 40-nm process |
|---|---|
| Supply Voltage | 0.9 V |
| Core Logic Performance Improvement | Up to 50% faster than Stratix IV FPGA prototype |
| Power Consumption Reduction | Typically 50% from Stratix IV FPGA prototype |
| Transceivers (GX Family) | Up to 36 full-duplex CDR-based transceivers |
| Transceiver Data Rate (GX Family) | Up to 6.5 Gbps |
| Dedicated RAM (GX Family) | 20,736 Kbits |
| Dedicated RAM (E Family) | 18,792 Kbits |
| User I/O Pins | Up to 880 |
HardCopy IV devices offer core logic performance up to 50% faster and typically 50% lower power consumption compared to their Stratix IV FPGA prototypes.
The Quartus II software provides a complete set of tools for designing both Stratix IV FPGA prototypes and HardCopy IV ASICs.
The family contains two variants: HardCopy IV Gx transceiver ASICs optimized for high-speed links, and HardCopy IV E ASICs optimized for logic and DSP functions.