This document is Volume 1 of the HardCopy III Device Handbook, providing an overview of device interfaces and integration. HardCopy III devices are Altera's low-cost, high-performance, low-power ASICs with pin-outs, densities, and architectures that complement Stratix III devices.
The HardCopy III device family consists of low-cost, high-performance, and low-power Application-Specific Integrated Circuits (ASICs) from Altera. These devices are designed to complement Stratix III FPGAs by offering functionally and electrically equivalent features such as phase-locked loops (PLLs), embedded memory, and I/O elements.
Fully tested production-quality samples are typically available 14 weeks from the date of your design submission.
Core logic performance can be up to 50% faster than the Stratix III FPGA prototype.
Power consumption is reduced by typically 50% or greater from the Stratix III FPGA prototype.