Altera EP4SGX180 Stratix IV GX Device Pin Information

This document describes the bank number VREF pin names and functions for different models, as well as configuration functions and channel information.

Brand: Altera
Document type: Datasheet
Language: English
Pages: 18
File format: PDF
File size: 100 KB
Published: 01 August, 2012
Updated: 29 September, 2023
MD5 checksum: 823E2B97075433A1191C35528DEA2812
PDF: Altera EP4SGX180 Stratix IV GX Device Pin Information PDF

About this manual

This document provides pin information for the Stratix IV GX EP4SGX180 device. It includes a pictorial representation of the device package showing the placement of various signal banks and reference voltages.

What's inside

Pin Information
Bank Diagram
PLL Pins
Reference Voltage Pins
JTAG Pins
Revision History

Frequently asked questions

What is the specific device model covered by this pin information?

This document provides pin information for the Stratix IV GX EP4SGX180 Device.

What is the version number of this document?

The current version of this document is Version 1.1.

What changes were made in Version 1.1 compared to Version 1.0?

Version 1.1 added bank numbers for JTAG pins, updated Note (1) in the Pin List, and grouped nCSO, ASDO, and DCLK into dedicated configuration/JTAG pins.

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