NDS352AP P-Channel Logic Level Enhancement Mode Field Effect Transistor Product Features
This document is a technical datasheet for the Fairchild Semiconductor NDS52AP, a P-channel logic level enhancement mode power field-effect transistor (FET). The device utilizes proprietary high cell density DMOS technology to achieve extremely low on-state resistance and is designed for low voltage applications such as notebook computer power management and portable electronics. It features an industry standard SOT-23 surface mount package using the SuperSOT™-3 design.
The datasheet provides absolute maximum ratings, electrical characteristics including off and on state parameters, dynamic characteristics like capacitance, switching characteristics, and typical performance curves for resistance variation with temperature and current.
| Drain-Source Voltage | -30 V |
|---|---|
| On-Resistance (Typical) | 0.5 Ω @ Vgs = -4.5V |
| Operating Temperature Range | -55 to 150 °C |
| Package Type | SuperSOT-3 (SOT-23) |
The device supports a maximum continuous drain current of -0.9 A and a maximum pulsed drain-source diode forward current of -10 A.
The device operates and stores within a temperature range of -55 to 150 °C.
The thermal resistance, junction-to-ambient, is 250 °CiW when mounted on a 0.02 in² pad of 20z copper.