This data sheet provides data for the MC10E/100E256, including pin definitions, function table and logic diagram.
This datasheet describes the MC10E256 and MC100E256, which contain three 4:1 multiplexers followed by transparent latches with differential outputs. The devices feature separate select controls for the leading 2:1 mux pairs and include a Master Reset (MR) to set outputs LOW.
Key specifications include a maximum delay from data to output of 950ps and a maximum delay from Latch Enable to output of 850ps. The MC100E variant supports an extended VEE range of -4.2V to -5.46V. The document provides logic diagrams, DC and AC characteristics, and outline dimensions for the 28-lead PLCC package.
| Max D to Output Delay | 950ps |
|---|---|
| Max LEN to Output Delay | 850ps |
| MC100E VEE Range | -4.2V to -5.46V |
| Input Pulldown Resistors | 75kQ |
| Package Type | 28-Lead PLCC |
The Master Reset overrides all other controls to set the Q outputs LOW.
The latch is transparent when the Latch Enable (LEN) is LOW.