MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. It features a maximum clock-to-output delay, dual differential outputs, master reset, and scan output.
The MC10E212 and MC100E212 are 3-bit scannable registered ECL drivers designed primarily as fan-out memory address drivers for ECL cache driving in VLSI array-based CPU designs. These devices utilize an input shift register with control logic to facilitate boundary scan applications, allowing users to conserve array output cell functionality and output pins.
| Max. CLK to Output | 1025ps |
|---|---|
| Package Type | 28-Lead PLCC |
| Supply Voltage Range (100E) | -4.2V to -5.46V |
| Input Pulldown Resistors | 75kQ |
| Power Supply Current (10E) | 80 mA (typ) |
The maximum clock to output delay is 1025ps.
The MC100E212 operates with an extended voltage range of -4.2V to -5.46V.
The MC10E212 and MC100E212 are available in a 28-Lead PLCC package.