The MC10E1651 is functionally and pin-for-pin compatible with the MC1651 in the MECL III family, but is fabricated using Motorola’s advanced MOSAIC III process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output compatibility with 10KH logic devices. In addition, a latch is available allowing a sample and hold function to be performed. The device is available in both a 16-pin DIP and a 20-pin surface mount package. The latch enable (LENa and LENb) input pins operate from standard ECL 10KH logic levels. When the latch enable is at a logic high level the MC10E1651 acts as a comparator, hence Q will be at a logic high level if V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state providing the latch enable setup and hold time constraints are met.
The Motorola MC10E1651 is a dual ECL output comparator with latch designed for the MECL III family. It is fabricated using Motorola's advanced MOSAIC III process and incorporates a fixed level of input hysteresis. The device is functionally and pin-for-pin compatible with the MC1651 but offers output compatibility with 10KH logic devices. It includes a latch feature that allows a sample and hold function to be performed when the latch enable input goes to a low logic level.
| Bandwidth | Typ. 3.0 dB |
|---|---|
| Propagation Delay | Typ. 775 ps |
| Output Rise/Fall Time | Typ. 350 ps |
| Common Mode Range | -2.0 V to +3.0 V |
| Input Hysteresis | Typ. 27 mV |
| Input Capacitance (DIP) | 3 pF |
| Input Capacitance (PLCC) | 2 pF |
It is functionally and pin-for-pin compatible with the MC1651 in the MECL III family.
The device is fabricated using Motorola's advanced MOSAIC III process.
The device is available in both a 16-pin DIP and a 20-pin surface mount package.