The MC10E/100E193 is an error detection and correction (EDAC) circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also provided at the PGEN pin, after Odd/Even parity control and gating with the BPAR input. This output also feeds to a 1-bit shiftable register, for use as part of a scan ring. Used in conjunction with 12-bit parity generators such as the E160, a SECDED (single error correction, double error detection) error system can be designed for a multiple of an 8-bit word.
The document describes the MC10E193 and MC100E193, which are error detection and correction (EDAC) circuits designed to generate modified Hamming parity codes for 8-bit words. These devices provide whole word parity outputs and include a scannable parity register suitable for use in SECDED systems.
| Package Type | 28-Lead PLCC (Case 776-02) |
|---|---|
| Operating Voltage Range (100E Series) | -4.2V to 5.46V |
| Input Pulldown Resistors | 75kQ |
| Propagation Delay (B to P1-P4) | 350 ns typ @ 25C |
| Power Supply Current (IEE) | 112 mA typ @ 25C |
The circuit generates modified Hamming parity codes on an 8-bit word.
Yes, it can be designed for a SECDED (single error correction, double error detection) system.