The MC10E/100E195 is a programmable delay chip designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The chip offers high resolution and frequency, allowing for very accurate system clock timing selectable entirely from a digital input.
The Motorola MC10E195 and MC100E195 are programmable delay chips (PDC) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition using a chain of gates with programmable delays of 1.25 and 1.5 times the basic gate delay. The device operates at frequencies greater than 1.0 GHz while maintaining over 600 mV of output swing.
| Bandwidth | >1.0 GHz |
|---|---|
| Output Swing | over 600 mV |
| Delay Resolution | approximately 20 ps |
| Worst Case Delay Range | 2.0 ns |
| Propagation Delay (IN to Q) | 1210 ps (Typ) |
It is designed primarily for clock de-skewing and timing adjustment.
The required device delay is selected by the seven address inputs D[0:6], which are latched on chip by a high signal on the latch enable (LEN) control.
Yes, an eighth latched input, D7, is provided for cascading multiple PDCs for increased programmable range.