The MC10E196 and MC100E196 are programmable delay chips (PDC) designed primarily for very accurate differential ECL input edge placement applications. The delay section consists of a chain of gates and a linear ramp delay adjust organized as shown in the logic symbol. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80 ps.
The required device delay is selected by the seven address inputs D[0:6], which are latched on chip by a high signal on the latch enable (LEN) control. An eighth latched input, D7, is provided for cascading multiple PDC's for increased programmable range. The FTUNE input takes an analog voltage and applies it to an internal linear ramp for reducing the 20 ps resolution still further.
| Worst Case Delay Range | 2.0ns |
|---|---|
| Delay Step Resolution | ~20ps |
| Bandwidth | >1.0GHz |
| Input Pulldown Resistors | 75KQ |
| Package Type | PLASTIC PACKAGE CASE 776-02 |
| Package Type | 28-Lead PLCC |
| Power Supply Current (100E) | 150 mA |
It is designed primarily for very accurate differential ECL input edge placement applications.
The required device delay is selected by the seven address inputs D[0:6], which are latched on chip by a high signal on the latch enable (LEN) control.
The FTUNE input takes an analog voltage and applies it to an internal linear ramp for reducing the 20 ps resolution still further.
An eighth latched input, D7, is provided for cascading multiple PDC's for increased programmable range.