The MC10E/100E167 is a 6-bit 2:1 multiplexer with single-ended outputs. Input data is selected by the Select control (SEL) and transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2. A HIGH on the Master Reset (MR) pin asynchronously forces all Q outputs LOW.
This document is a technical datasheet for the Motorola MC10E167 and MC100E167 integrated circuits. The device contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Data selection is controlled by the SEL pin, while data transfer occurs on the positive edge of CLK1 or CLK2 clocks.
| Operating Frequency (Min) | 1000MHz |
|---|---|
| Clock to Output Delay (Max) | 800ps |
| Package Type | 28-Lead PLCC |
| Supply Voltage Range (100E) | -4.2V to -5.46V |
A HIGH on the Master Reset (MR) pin asynchronously forces all Q outputs LOW.
The selected data are transferred by a positive edge on CLK1 or CLK2.