The MC10E/100E193 is an error detection and correction (EDAC) circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also provided at the PGEN pin, after Odd/Even parity control and gating with the BPAR input. This output also feeds to a 1-bit shiftable register, for use as part of a scan ring. Used in conjunction with 12-bit parity generators such as the E160, a SECDED (single error correction, double error detection) error system can be designed for a multiple of an 8-bit word.
The MC10E193 and MC100E193 are error detection and correction (EDAC) circuits designed to generate modified Hamming parity codes for 8-bit words. The circuit provides parity for the whole word at the P5 output and supports a scannable parity register. When used with 12-bit parity generators like the E160, it enables the design of a Single Error Correction, Double Error Detection (SECDED) system.
| Package Type | 28-Lead PLCC |
|---|---|
| Package Case Number | 776-02 |
| Operating Temperature Range | 0°C to 85°C |
| Input HIGH Current (Typical) | 150 uA |
| Propagation Delay (Bto P1-P4) | 350 ns (Typical) |
| Propagation Delay (Bto P5) | 400 ns (Typical) |
It is an error detection and correction (EDAC) circuit that generates modified Hamming parity codes on an 8-bit word.
Yes, when used with 12-bit parity generators such as the E160, it can design a SECDED (single error correction, double error detection) error system.
The 100E version supports an extended VEE range from -4.2V to 5.46V.