The MC10E/100E150 is a 6-bit D latch with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master Reset (MR) overrides all other controls to set the Q outputs low.
This document provides technical data for the MC10E150 and MC100E150, a family of 6-bit D-type latches featuring differential outputs. The device includes six latches controlled by Latch Enables (LEN1, LEN2) and a Master Reset (MR), with propagation delays as low as 800ps maximum.
| Number of Latches | 6 |
|---|---|
| Max Propagation Delay | 800ps |
| Operating Voltage Range (100E) | -4.2V to -5.46V |
| Input Pulldown Resistors | 75kQ |
| Package Type | 28-Lead PLCC |
The Master Reset overrides all other controls to set the Q outputs low.
Latches are transparent when both Latch Enables (LEN1, LEN2) are LOW.