The MC10E/100E160 is a 12-bit parity generator/checker. When the number of input highs is odd, the Q output is high. A high on the Enable input (EN) forces the Q output low. The E160 also features an output register. Multiplexers direct the register input, giving the option of holding present data by asserting HOLD LOW, or of shifting data in through the S-IN pin by asserting SHIFT HIGH. The output register itself is clocked by a positive edge on CLK1 or CLK2 (or both). A high on the reset pin (R) overrides to force the Y output low.
This document is a technical datasheet for the Motorola MC10E160 and MC100E160 integrated circuits. These devices function as 12-bit parity generators and checkers, featuring a shiftable output register with hold capability. The MC100E160 variant supports an extended VEE voltage range from -4.2V to -5.46V.
| Function | 12-bit parity generator/checker |
|---|---|
| Max D to Q Output | 900ps |
| Package Type | 28-Lead PLCC |
| VEE Range (MC100E) | -4.2V to -5.46V |
The Q output goes HIGH when an odd number of inputs are HIGH.
A HIGH on the Enable input forces the Q output LOW.
The maximum D to Q/Q output delay is 900ps.