MC10E/100E156 is 3-BIT 4:1 MUX-LATCH, includes three 4:1 multiplexers, followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.
The MC10E156/MC100E156 is a 3-bit 4:1 Mux-Latch device containing three 4:1 multiplexers followed by transparent latches with differential outputs. The device features asynchronous master reset, dual latch enables, and extended 100E VEE range. It is available in a 28-lead PLCC package.
| Max. D to Output MUX-Latch | 950ps |
|---|---|
| Max. LEN to Output | 850ps |
| Package Type | 28-Lead PLCC |
| Input Pulldown Resistors | 75kQ |
The Master Reset overrides all other controls to set the Q outputs LOW.
The latch is transparent when both Latch Enables (LEN1, LEN2) are LOW.
The maximum propagation delay from data to output is 950ps.