The DS90CF363 is a 3.3V LVDS transmitter, 18-bit Flat Panel Display (FPD) link - 65 MHz. It converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 170 Mbytes/sec. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
The DS90CF363 is an LVDS transmitter chipset designed to convert 21 bits of CMOS or TTL input data into three LVDS data streams and one parallel transmit clock. Operating at a frequency up to 65 MHz, it supports resolutions including XGA (1024x768) with a total throughput of up to 1.3 Gbps.
| Supply Voltage | 3.3V |
|---|---|
| Max Shift Clock Frequency | 65 MHz |
| Data Throughput | 1.3 Gbps |
| Bandwidth | 170 Mbytes/sec |
| Operating Temperature Range | -40°C to +85°C |
| Package Type | 48-lead TSSOP |
The transmitter supports a transmit clock frequency of 65 MHz.
The chipset power consumption is less than 250 mW in typical operation.