National Semiconductor DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface Datasheet

The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 784Mbps, providing a total throughput of 5.7Gbps (714 Megabytes per second). The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive. To increase bandwidth, the maximum pixel clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. The DS90C387A transmitter provides a second LVDS output clock. Both LVDS clocks are identical. This feature supports backward compatibility with the previous generation of FPD-Link Receivers - the second clock allows the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit FPD-Link receivers. This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications.


National Semiconductor DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface Datasheet - cover page
Brand
National Semiconductor
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
19
File format
PDF
File size
394 KB
Published
04 July, 2012
Updated
29 September, 2023
MD5 checksum
6855877494306C1455613D92D37A22FE

About this manual

The DS90C387A/DS90CF388A chipset is a transmitter/receiver pair designed to support dual pixel data transmission between a host and a flat panel display up to QXGA resolutions. The transmitter converts 48 bits of CMOS/TTL data and 3 control bits into 8 LVDS data streams, achieving a maximum dual pixel rate of 112MHz and a total throughput of 5.7Gbps. This chipset offers higher bandwidth support and longer cable drive compared to prior generations of FPD-Link devices.

What's inside

  • General Description
  • Features
  • Absolute Maximum Ratings
  • Electrical Characteristics
  • Transmitter Input Characteristics
  • Transmitter Switching Characteristics
  • Receiver Switching Characteristics

Specifications

Maximum Dual Pixel Rate112MHz
Total Throughput5.7Gbps
Junction Temperature+150°C
BandwidthUp to 5.7 Gbps

Frequently asked questions

What resolutions does the DS90C387A/DS90CF388A support?

The chipset supports SVGA through QXGA panel resolutions.

What is the maximum pixel clock rate?

The maximum pixel clock rate is increased to 112 MHz.

Is the device backward compatible with previous FPD-Link devices?

Yes, it is backward compatible with the previous generation of FPD-Link Receivers.

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