IDT RC64474/RC64475 Datasheet

This document describes the features and characteristics of IDT's products, including high-performance 64-bit microprocessor, single/double precision floating-point unit, high-speed caches, and flexible bus interface.


IDT RC64474/RC64475 Datasheet - cover page
Brand
IDT
Category
microcontrollers
Document type
Datasheet
Language
English
Pages
25
File format
PDF
File size
373 KB
Published
05 June, 2012
Updated
29 September, 2023
MD5 checksum
6706B588D07C6878CA6351A8E039D39A

About this manual

The IDT RC64474 and RC64475 are high-performance 64-bit microprocessors based on the RISCore4000 core, designed for applications requiring high bandwidth and real-time response. These processors implement the MIPS-III Instruction Set Architecture (ISA) and feature a single-cycle ALU with an autonomous multiply/divide unit.

What's inside

  • Features
  • Device Overview
  • Implementation of MIPS-III architecture
  • RISCore4000/RISCore5000 Family
  • Secure user processing environment
  • Memory Management Unit (MMU)
  • Development Tools
  • Cache Memory

Specifications

Architecture64-bit microprocessor, based on RISCore4000
Performance (MIPS)330 Dhrystone MIPS at 250 MHz
Floating Point Performance125 peak MFLOP/s at 250 MHz
Instruction Cache Size16KB two-way set associative
Data Cache Size16KB two-way set associative
External Bus Width (RC64474)32-bit
External Bus Width (RC64475)64-bit
Operating Voltage3.3V core with 3.3V VO

Frequently asked questions

What is the instruction set architecture?

The processors implement the MIPS-III Instruction Set Architecture (ISA).

Is there a migration path from RC4640/RC4650?

Yes, the processors offer a direct migration path through full pin and socket compatibility.

What is the peak instruction bandwidth?

The instruction cache provides a peak instruction bandwidth of 1000MB/sec at 250MHz.

Download PDF (373 KB)

More IDT Manuals


View all IDT manuals →