The IDT71V2576/78 are high-speed SRAMs organized as 128K x 36/256K x 18. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle.
This document is a technical datasheet for the IDT71V2576/78 series of high-speed Synchronous Static RAMs (SRAMs). These devices are organized as 128K x 36 or 256K x 18 and feature pipelined outputs, a burst counter, and single cycle deselect functionality. They operate with a 3.3V core power supply and 2.5V I/O voltage.
| Memory Configuration | 128K x 36, 256K x 18 |
|---|---|
| Core Power Supply Voltage | 3.3V (Min: 3.135V, Max: 3.465V) |
| I/O Power Supply Voltage | 2.5V (Min: 2.375V, Max: 2.625V) |
| Maximum Operating Frequency | 150MHz (Commercial), 133MHz (Industrial) |
| Clock Access Time (Commercial) | 3.8ns at 150MHz |
| Package Types | TQFP, BGA (119 ball), BGA (165 fine pitch) |
The device supports 128K x 36 and 256K x 18 memory configurations.
Yes, it supports high system speed with a Burst Counter and Single Cycle Deselect feature.