IDT IDT71P72104 QDRII SRAM Datasheet

IDT71P72204 is a 18Mb dual-channel QDR™II SRAM chip produced by IDT company. The chip has 18Mb storage capacity, supports DDR (double data rate) multiplexed address bus, supports 2-Word Burst, and can achieve 2 data ports simultaneously reading and writing operations, providing up to 4 data bytes per clock cycle. Data transfer rate.


IDT IDT71P72104 QDRII SRAM Datasheet - cover page
Brand
IDT
Category
Memory
Document type
Datasheet
Language
English
Pages
22
File format
PDF
File size
593 KB
Published
06 June, 2012
Updated
30 September, 2023
MD5 checksum
8FF2730494EB13763757BC269D074E86

About this manual

The document describes the IDT71P72104, a high-speed synchronous memory device belonging to the QDRII family. It features an 18Mb density with configurations of 2Mx9 bits, supporting concurrent transactions via separate independent read and write data ports.

Key characteristics include dual-echo clock outputs (CQ and CQ) for precise downstream timing, HSTL inputs scalable from 1.4V to 1.9V, and a single DDR multiplexed address bus. The device operates with a 1.8V core voltage and is packaged in a 165-ball fBGA.

What's inside

  • Features
  • Functional Block Diagram
  • Clocking
  • DLL Operation
  • Echo Clock
  • Read and Write Operations
  • Output Enables
  • Programmable Impedance

Specifications

Density18Mb (2Mx9, 2Mx8, 1Mx18, 512kx36)
InterfaceHSTL(1.5V)
Core Voltage1.8V (VDD)
Package165-ball fBGA

Frequently asked questions

What is the core voltage of the IDT71P72104?

The device operates with a 1.8V core voltage (VDD).

What is the core voltage required for this SRAM?

The device requires a 1.8V core voltage (VDD).

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