IDT74GTLP16612 is an 18-bit universal bus transceiver that provides signal level translation from TTL to GTLP for applications requiring a high-speed interface between cards operating at TTL logic levels and back-planes operating at GTLP logic levels.
The IDT74GTLP16612 is a CMOS 18-bit universal bus transceiver designed to provide signal level translation from TTL to GTLP. It facilitates high-speed interfaces between cards operating at TTL logic levels and backplanes operating at GTLP logic levels, incorporating internal edge-rate control that is process, voltage, and temperature (PVT) compensated.
The device features bidirectional data flow with D-type latches and flip-flops supporting transparent, latched, or clocked modes. It includes a VREF pin for receiver threshold reference and an Edge Rate Control Circuit to reduce output noise. The transceiver is available in SSOP and TSSOP packages and operates over an industrial temperature range of -40°C to +85°C.
| Number of Channels | 18-bit |
|---|---|
| Operating Temperature Range | -40°C to +85°C |
| Output Current (A-Port) | +/- 32mA |
| Max Clock Frequency | 175 MHz |
| Package Types | SSOP and TSSOP |
It provides signal level translation from TTL to GTLP.
No, it includes Bus-Hold to eliminate the need for external pull-up resistors.
It provides a reference voltage for the receiver threshold.