The HD74HCT563/HD74HCT573 are octal transparent latches with 3-state outputs. When the latch enable (LE) input is high, the Q outputs of the HD74HCT563 will follow the inversion of the D inputs, while the Q outputs of the HD74HCT573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enabled returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
This document is a technical datasheet for the Hitachi HD74HCT563 and HD74HCT573 integrated circuits. These are octal transparent latches with 3-state outputs designed for LSTTL and CMOS output logic level compatibility. The devices operate at high speeds with a typical propagation delay of 13 ns and support a wide operating voltage range from 4.5 V to 5.5 V.
| Propagation delay (Data to Q) | 13 ns typ |
|---|---|
| Operating voltage range | 4.5 to 5.5 V |
| Low input current (max) | 1 uA max |
| Quiescent supply current (static) | 4 uA max |
| High output current fanout | 15 LSTTL Loads |
When LE is high, Q outputs follow the inversion of D inputs for HD74HCT563 and follow D inputs directly for HD74HCT573.
All outputs go to a high impedance state regardless of other signals.