This document describes the features and characteristics of IDT72261LA and IDT72271LA CMOS SuperSync FIFOs, including memory organizations, read/write cycle time, data latency time, low power mode, reset functions, data status flags, etc.
The IDT72261LA/IDT72271LA are exceptionally deep, high-speed CMOS First-In-First-Out (FIFO) memories with clocked read and write controls. These devices offer numerous improvements over previous SuperSync FIFOs, including the removal of frequency limitations between input clocks and a fixed, low first word data latency time for retransmit operations.
The datasheet details two timing modes of operation: IDT Standard mode and First Word Fall Through (FWFT) mode. It describes five flag pins used to signal FIFO status, such as Empty/Full/Half-Full flags, and explains how programmable Almost-Empty and Almost-Full flags can be set via serial or parallel means.
| Memory Organization IDT72261LA | 16,384 x 9 |
|---|---|
| Memory Organization IDT72271LA | 32,768 x 9 |
| Read/Write Cycle Time | 10ns |
| Access Time | 8ns |
| Package Type | 64-pin Thin Quad Flat Pack (TQFP) and 64-pin Slim Thin Quad Flat Pack (STQFP) |
| Technology | High-performance submicron CMOS technology |
The IDT72261LA has a 16,384 x 9 organization and the IDT72271LA has a 32,768 x 9 organization.
The devices feature a 10ns read/write cycle time with an 8ns access time.
These FIFOs have five flag pins: EF/OR, FF/R, HF, PAE, and PAF.