This document is a functional block diagram of DSC-5632/3 published by Integrated Device Technology, Inc. in November 2003. It includes features such as busy and interrupt flags, on-chip port arbitration logic, full on-chip hardware support of semaphore signaling between ports, fully asynchronous operation from either port, separate byte controls, dual-port memory cells, high performance and high reliability.
The document details the IDT70T651/9S, a high-speed 256K x 36 Asynchronous Dual-Port Static RAM designed for use as a stand-alone memory or in Master/Slave configurations. It supports both commercial and industrial temperature ranges with access times of up to 15ns.
| Capacity | 256/128K x 36 |
|---|---|
| Access Time (Commercial) | 8/10/12/15ns |
| Access Time (Industrial) | 10/12ns |
| Power Supply (Core) | 2.5V (+/-100mV) |
The maximum access time for commercial grade devices is 15ns.
Yes, it includes a RapidWrite Mode to simplify high-speed consecutive write cycles.