Update: 30 September, 2023
The IDT71V3577/79 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data, address and control registers. There are no registers in the data output path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V3577/79 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter tracks the address during burst mode to ensure that data is provided to the system during the burst.
File format: PDF
Size: -
MD5 Checksum: 18474944EA5644C9E20BB93222AF46E2
Publication date: 05 June, 2012
Downloads: -
PDF Link: IDT IDT71V3577S/IDT71V3579S/IDT71V3577SA/IDT71V3579SA handbook PDF