Lattice ispLSI 5256VA Datasheet

ispLSI ® 5256VA In-System Programmable 3.3V SuperWIDE™ High Density PLD is a high-density, high-performance, low-power PLD with 12000 PLD gates/256 macrocells, powered by a 3.3V power supply, supports 3.3V/2.5V selectable I/O, has up to 192 I/O pins, 256 registers, and high-speed global interconnects.


Lattice ispLSI 5256VA Datasheet - cover page
Brand
Lattice
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
25
File format
PDF
File size
237 KB
Published
06 June, 2012
Updated
30 September, 2023
MD5 checksum
88A79647FD7F592AC70B48EB6602293D

About this manual

The ispLSI 5256VA is a high-density, in-system programmable logic device (PLD) utilizing 3.3V SuperWIDE technology. It features 12,000 PLD gates and 256 macrocells, operating with a maximum frequency of 125 MHz.

What's inside

  • ispLSI 5000V Description
  • Architecture Features
  • Specifications ispLSI 5256VA
  • Functional Block Diagrams
  • Global Clock Distribution
  • Boundary Scan Register Circuit

Specifications

PLD Gates12000
Macrocells256
I/O PinsUp to 192
Registers256
Maximum Operating Frequency125 MHz
Propagation Delay7.5 ns

Frequently asked questions

What is the power supply voltage?

The device operates from a 3.3V power supply.

Is the device reprogrammable after soldering?

Yes, it is in-system programmable for faster debugging and improved product quality.

Does the device support boundary scan testing?

Yes, it is 100% IEEE 1149.1 Boundary Scan Testable.

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