This document describes the features and characteristics of the MACH 4 CPLD family, which includes high-performance E2CMOS® programmable logic with flexible architecture, high speed, and programmability.
The MACH 4 family from Lattice provides a flexible, high‑performance CPLD solution with 3.3‑V and 5‑V operation, JTAG and PCI compliance, and a range of package options. It supports densities from 32 to 256 macrocells with 100 % routability and pin‑out retention.
The manual covers functional description, architectural details, macrocell operation, package and I/O options, device features, and ordering information for both commercial and industrial grades.
| Supply Voltage | 3.3 V & 5 V |
|---|---|
| tPD (Commercial) | 7.5 ns |
| tPD (Industrial) | 10 ns |
| Maximum Clock Frequency (fCNT) | 111.1 MHz |
| JTAG Compliant | Yes |
| PCI Compliant | Yes |
| Package Types | PLCC, PQFP, TQFP, BGA |
MACH 4 devices are offered in both 3.3‑V and 5‑V versions.
The commercial tPD timing is 7.5 ns.
Yes, MACH 4 devices support JTAG (IEEE 1149.1) compliance.
The family is available in PLCC, PQFP, TQFP, and BGA packages ranging from 44 to 256 pins.