The SY10/100E337 is a 3-bit registered bus transceiver with scan designed for use in new, high-performance ECL systems. It features a maximum clock to bus (data transmit) of 1500ps, a maximum clock to Q (data receive) of 1000ps, an extended 100E VEE range of –4.2V to –5.5V, 25Ω cutoff bus outputs, 50Ω receiver outputs, etc.
This handbook describes the SY10E337 and SY100E337 3‑bit scannable registered bus transceivers, highlighting features such as 25 Ω bus outputs, 50 Ω receiver outputs, scan mode operation, and compatibility with industry‑standard ECL levels. It includes functional block diagrams, pin‑out tables, and detailed timing and electrical parameters.
The document also lists package information (28‑pin PLCC J28‑1), ordering codes for commercial versions, and safety notices. Electrical characteristics cover output voltage levels, input currents, propagation delays, and setup/hold times for both bus and receive paths.
| Bus output cutoff voltage | -2.10 V |
|---|---|
| Input HIGH current | 150 µA |
| Propagation delay CLK to Q | 450‑1000 ps |
| Bus output impedance | 25 Ω |
| Receiver output impedance | 50 Ω |
The bus outputs are designed for a 25 Ω bus.
It is supplied in a 28‑pin PLCC (J28‑1) package.
Typical propagation delay from CLK to Q is 450 ps, with a maximum of 1000 ps.