The document describes a 3-bit 4:1 multiplexer-latch called SY10/100E256, which has features such as extended VEE range, separate select controls, differential outputs, and full compatibility with industry standard 10KH, 100K ECL levels.
The SY10E256 and SY100E256 are 3‑bit 4:1 multiplexers with latch functions, offering differential outputs and separate select controls for high‑performance ECL systems. The device includes a master reset that forces all Q outputs low and a latch enable that controls transparency.
The document details the block diagram, pin configuration, truth table, AC/DC electrical characteristics, propagation delays, setup/hold times, and product ordering codes for the 28‑lead PLCC (J28‑1) package.
| SEL1 Propagation Delay (min) | 550 ps |
|---|---|
| SEL2 Propagation Delay (min) | 450 ps |
| LEN Propagation Delay (min) | 350 ps |
| Input HIGH Current (IIH) | 150 µA |