The SY10/100E336 is a bus transceiver designed for use in new, high-performance ECL systems. It features a 25Ω cutoff bus output, an extended -4.2V to -5.5V VEE range, a 50Ω receiver output, transmit and receive registers, a maximum clock to bus of 1500ps, a maximum clock to Q of 1000ps, internal edge slow-down capacitors on bus outputs, additional package ground pins, full compatibility with industry standard 10KH, 100K ECL levels, internal 75KΩ input pulldown resistors, and full compatibility with Motorola MC10E/100E336. It is available in a 28-pin PLCC package.
The SY10E336/SY100E336 family are three‑bit registered bus transceivers with both transmit and receive registers, designed for high‑performance ECL systems. They drive 25 Ω bus lines and provide 50 Ω receiver outputs, with cutoff low level at –2.0 V and full compatibility with industry‑standard 10KH and 100K ECL levels.
Key specifications include a supply voltage range of –4.2 V to –5.5 V, maximum clock‑to‑bus delay of 1500 ps, maximum clock‑to‑Q delay of 1000 ps, and availability in a 28‑lead PLCC (J28‑1) package. Ordering codes such as SY10E336JC, SY10E336JCTR, SY100E336JC and SY100E336JCTR are listed.
| Receiver output impedance | 50 Ω |
|---|---|
| Cutoff output voltage | –2.0 V |
| Supply voltage range | –4.2 V to –5.5 V |
| Maximum clock‑to‑bus delay | 1500 ps |
| Maximum clock‑to‑Q delay | 1000 ps |
| Package type | 28‑lead PLCC (J28‑1) |
It is fully compatible with industry standard 10KH and 100K ECL levels.
The family offers three bus transceivers, each with transmit and receive registers.
They are supplied in a 28‑lead PLCC (J28‑1) package.
The ordering codes are SY100E336JC and SY100E336JCTR.