The MAX12528 is a dual 80Msps, 12-bit analog-to-digital converter (ADC) featuring fully differential wideband track-and-hold (T/H) inputs, driving internal quantizers. The MAX12528 is optimized for low power, small size, and high dynamic performance in intermediate frequency (IF) and baseband sampling applications. This dual ADC operates from a single 3.3V supply, consuming only 726mW while delivering a typical 69.8dB signal-to-noise ratio (SNR) performance at a 175MHz input frequency. The T/H input stages accept single-ended or differential inputs up to 400MHz. In addition to low operating power, the MAX12528 features a 330µW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX12528 to use the internal 2.048V bandgap reference or accept an externally applied reference and allows the reference to be shared between the two ADCs. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.15V. The MAX12528 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX12528 supports either a single-ended or differential input clock. User-selectable divide-by-two (DIV2) and divide-by-four (DIV4) modes allow for design flexibility and help eliminate the negative effects of clock jitter. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (D
The MAX12528 is a dual‑channel, 80 Msps, 12‑bit analog‑to‑digital converter optimized for low power, small size, and high dynamic performance in IF and baseband applications. It operates from a single 3.3 V supply and includes features such as fully differential inputs, selectable clock division, and a power‑down mode.
Key specifications include a 68‑pin thin QFN package (10 mm × 10 mm × 0.8 mm), 726 mW typical power consumption in single‑ended mode, 330 µW in power‑down, 750 MHz input bandwidth, and output data selectable as two’s complement or Gray code. The device supports both single‑ended and differential input clocks with DIV2 and DIV4 options, and provides common‑mode reference to simplify differential designs.
| Sampling Rate | 80 Msps |
|---|---|
| Supply Voltage | 3.3 V |
| Power‑down Mode Consumption | 330 µW |
| Package | 68‑pin thin QFN 10 mm × 10 mm × 0.8 mm |
| Input Bandwidth | 750 MHz |
| Digital Output Format | Two’s complement or Gray code |
| Clock Division Options | DIV2 and DIV4 |
The MAX12528 consumes only 330 µW in power‑down mode.
The device can output data in either two’s complement or Gray code.
It is supplied in a 68‑pin thin QFN package measuring 10 mm × 10 mm × 0.8 mm.