This file is the product manual for PI7C7300A 3-PORT PCI-to-PCI BRIDGE
This manual provides a detailed description of the Pericom PI7C7300A 3‑Port PCI‑to‑PCI bridge, including its block diagram, signal definitions, and bus operation. It explains address decoding, transaction ordering, error handling, and exclusive access mechanisms for both primary and secondary PCI buses.
The document also covers configuration registers, bridge behavior, JTAG boundary‑scan controller, electrical and timing specifications, and includes an evaluation‑board user guide and a FAQ section that answers common integration questions.
| Supported Clock Frequency Combinations | 66 MHz, 50 MHz, 25 MHz (various primary/secondary mixes) |
|---|---|
| JTAG Signal Pins | TRST#, TCK, TMS, TDI, TDO with weak internal pull‑up |
The bridge supports primary, secondary‑1 and secondary‑2 clock frequencies of 66 MHz, 50 MHz, or 25 MHz in any of the listed combinations.
The JTAG signals (TRST#, TCK, TMS, TDI, TDO) have weak internal pull‑up resistors, so they need not be tied if the JTAG circuit is disabled; otherwise they should be connected according to the IEEE 1149 specification.