The GS8320EV18/32/36T is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter, which can be used in DSP main store, network chip set support and other applications.
The GS8320EV18/32/36T is a 37,748,736‑bit high‑performance synchronous SRAM originally developed for Level 2 cache applications and now used in DSP main stores and networking chipsets. It supports multiple configurations (18‑, 32‑, and 36‑bit data widths) and speeds ranging from 133 MHz to 250 MHz.
Key features include a user‑configurable FT pin for flow‑through or pipeline reads, Dual Cycle Deselect (DCD) operation, byte‑write and global‑write modes, automatic power‑down, and operation from a 1.8 V core supply. The device is supplied in a 100‑pin TQFP package, with a Pb‑free option available.
| Memory capacity | 37,748,736 bits |
|---|---|
| Maximum frequency | 250 MHz |
| Core voltage | 1.8 V |
| Package | 100‑Pin TQFP |
| Pb‑free package option | Available |
| FT pin function | Flow‑through or pipeline mode selection |
| DCD operation | Dual Cycle Deselect |
| Power‑down control | Automatic power‑down |
The device operates on a 1.8 V power supply.
It is offered in a 100‑pin TQFP package, with a Pb‑free version available.
Pull the FT pin low to place the RAM in Flow‑Through mode.
The SRAM can run up to 250 MHz, depending on the speed grade.