Key facts
- Brand
- GSI
- Model
- GS200
- Industry
- Industrial
- Documents
- 7
- Languages
- EN
- Last added
- 2012-06-08
Start here
GSI TECHNOLOGY GS88018/32/36AT-250/225/200/166/150/133 512K x 18 256K x 32 256K x 36 9Mb Sync Burst SRAMs
The GS88018/32/36AT is a high-performance synchronous static RAM (SRAM) designed for Level 2 Cache applications supporting high-performance CPUs. It features a 2-bit burst address counter and operates at frequencies ranging from 133 MHz to 250 MHz with core voltages of 2.5 V or 3.3 V.
Read onlineGSI GS200 specifications
| Capacity Options | 512K x 18, 256K x 32, 256K x 36 |
|---|---|
| Package Type | JEDEC-standard 100-lead TQFP |
| Operating Frequency Range | 250 MHz to 133 MHz |
| Core Voltage Options | 2.5 V or 3.3 V |
| I/O Voltage Compatibility | 2.5 V or 3.3 V |
All GSI GS200 documents by type
Day-to-day operation, settings and troubleshooting. Start here if the product is already set up.
Ratings, dimensions and ordering codes, for selection and design work.
- GSI TECHNOLOGY GS88018/32/36AT-250/225/200/166/150/133 512K x 18 256K x 32 256K x 36 9Mb Sync Burst SRAMs 26 p
- GSI TECHNOLOGY GS8320E18/32/36T-250/225/200/166/150/133 2M x 18 1M x 32 1M x 36 36Mb Sync Burst SRAMs 25 p
- GSI GS882ZV18/36BB/D-333/300/250/200 NBT SRAM Datasheet 33 p
- GSI TECHNOLOGY GS8320EV18/32/36T-250/225/200/166/150/133 handbook 24 p
- GSI Technology GS88237BB/D-333/300/250/200 Synchronous Burst SRAM Datasheet 29 p
- GSI TECHNOLOGY GS816018/32/36BT-250/200/150 handbook 24 p
Questions answered in these manuals
What is the primary application for this SRAM?
The device was originally developed for Level 2 Cache applications supporting high performance CPUs.
What is the default burst order mode?
The device defaults to Interleaved Pipeline mode.
What is the default burst mode?
The device defaults to Interleaved Pipeline mode.
What are the available burst modes?
The device supports Linear Burst Order and Interleaved Burst Order.
What does NBT stand for and what does it do?
NBT (No Bus Turn Around) functionality allows zero‑wait read‑write‑read bus utilization, eliminating turnaround cycles between read and write operations.
From: GSI GS882ZV18/36BB/D-333/300/250/200 NBT SRAM Datasheet
How is sleep mode activated on the SRAM?
Sleep mode is entered by pulling the ZZ pin high; after two clock cycles the device enters a low‑current power‑down state.
From: GSI GS882ZV18/36BB/D-333/300/250/200 NBT SRAM Datasheet