This document describes the features and characteristics of the GS82032AT/Q-180/166/133/100 64K x 32 2M Synchronous Burst SRAM produced by Giga Semiconductor, Inc.
The GS82032A is a 64K x 32-bit (2M bit) high-performance synchronous SRAM designed for applications ranging from DSP main stores to networking chipset support. It features a 2-bit burst address counter that can be configured for linear or interleaved burst modes via the LBO pin.
The device operates with a 3.3V core power supply and supports 2.5V or 3.3V I/O voltages. Key operating frequencies include 180 MHz, 166 MHz, 133 MHz, and 100 MHz. The chip includes user-configurable flow-through or pipelined operation via the FT pin and offers single-cycle deselect (SCD) functionality.
| Memory Capacity | 64K x 32 (2M bits) |
|---|---|
| Operating Frequency | 180 MHz - 100 MHz |
| Access Time | 8 ns - 12 ns |
| Core Voltage | 3.3 V (+/- tolerance) |
| I/O Voltage | 2.5 V or 3.3 V |
| Package Type | TQFP, QFP (100-lead) |
The device is available in versions operating at 180 MHz, 166 MHz, 133 MHz, and 100 MHz.
Yes, the Burst address counter may be configured to count in either linear or interleaved order with the Linear Burst Order (LBO) input.
Low power Sleep mode is attained through the assertion (high) of the ZZ signal, or by stopping the clock (CK).