This product has the characteristics of high density, high speed, low power consumption, flexible clock
The Delta39K ISR CPLD family offers high‑density programmable logic with 30 K to 200 K usable gates, 512 to 3072 macrocells, and up to 428 I/O pins. It includes embedded SRAM (80 K‑480 K bits) and dual‑port channel memory (16 K‑96 K bits), operates at up to 233 MHz, and supports multiple I/O voltage standards (3.3 V, 2.5 V, 1.8 V, 1.5 V) with low standby current.
The devices use a six‑layer 0.18‑µm CMOS process and feature a logic‑block‑cluster architecture with programmable interconnect matrix, dedicated clocks, and flexible macrocell functions. Programming is done in‑system via a JTAG‑compliant interface, and development is supported by Cypress Warp, Active‑HDL, and other tools. The family is PCI‑compliant, hot‑swap ready, and offers options such as Self‑Boot and AnyVolt voltage interfaces.
| Usable gates | 30K to 200K |
|---|---|
| Macrocells | 512 to 3072 |
| Embedded SRAM | 80K to 480K bits |
| Channel memory | 16K to 96K bits (dual‑port) |
| Maximum operating frequency | 233 MHz |
| Supported I/O voltages | 3.3 V, 2.5 V, 1.8 V, 1.5 V |
| Standby current | as low as 5 mA |
The Delta39K supports 3.3 V, 2.5 V, 1.8 V, and 1.5 V I/O voltage levels.
Programming is performed via a JTAG‑compliant on‑board interface using the In‑System Reprogrammable (ISR) feature.
The standby current can be as low as 5 mA.