The K4S280432M CMOS SDRAM is 128Mbit SDRAM organized as 4 x 8,388,608 words by 4 bits, fabricated with SAMSUNG's high performance CMOS technology.
This document describes the Samsung K4S280432M 128Mbit CMOS SDRAM, its features, organization, and functional block diagram. It includes ordering information for various package options and detailed pin configurations.
Technical data such as absolute maximum ratings, DC and AC operating conditions, IBIS specifications, and command timing tables are provided to aid designers in integrating the device into high‑performance memory systems.
| Memory density | 128 Mbit |
|---|---|
| Organization | 8M x 4-bit x 4 banks |
| Supply voltage (Vob, VDDQ) | 3.0 V min / 3.3 V typ / 3.6 V max |
| Maximum operating frequency (part K4S280432M‑TC/L80_) | 125 MHz (CL=3) |
| CAS latency options | 2 and 3 |
| Burst length options | 1, 2, 4, 8 |
| Power dissipation | 1 W |
The device operates from 3.0 V (minimum) to 3.6 V (maximum) with a typical voltage of 3.3 V.
The SDRAM supports CAS latency values of 2 and 3.
The K4S280432M‑TC/L80_ part can run up to 125 MHz (CL = 3).