IMSA110 is a 1-D/2-D software configurable convolution/filter. It has the following features: programmable line delays, 8-BIT data and 8.5-BIT coefficient slices, 21 multiply-and-accumulate stages, 1-D (21) or 2-D (3 x 7) convolution window, data transformation post processor, fully cascadable in window size and accuracy, 20 MHZ data throughput (420 MOPS), signed/unsigned data and coefficients, microprocessor interface, high speed CMOS implementation, TTL compatible, single +5V ± 10% supply, power dissipation <2.0 watts, 100 pin ceramic PGA.
The IMSA110 is a single‑chip, reconfigurable image and signal processing subsystem offering 21 multiply‑and‑accumulate stages that can be configured as a 1‑D 21‑stage filter or a 3 × 7 2‑D window. It provides 8‑bit data and 8.5‑bit coefficient slices, a 20 MHz data throughput (420 MOPS), and a fully cascaded architecture for building larger filters.
The device is supplied in a 100‑pin ceramic grid array (PGA100) package, operates from a single +5 V supply (±10 %), and dissipates less than 2 W. It includes three programmable shift registers (0‑1120 clock cycles), a backend post‑processor with shifter, cascade adder, rectifier, statistics monitor, and a data‑transformation unit with a 64‑word lookup table.