Industrial

The MC10E/MC100E336 is an integrated circuit that contains three bus transceivers with both transmit and receive registers.

The MC100LVE310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The LVE310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees. The MC100E310 is pin compatible to the National 100310 device. The MC100LVE310 works from a –3.3V supply while the MC100E310 provides identical function and performance from a standard –4.5V 100E voltage supply.

The MC100LVE310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The LVE310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees. The MC100E310 is pin compatible to the National 100310 device. The MC100LVE310 works from a –3.3V supply while the MC100E310 provides identical function and performance from a standard –4.5V 100E voltage supply.

The MC10E/100E256 is a 3-bit 4:1 multiplexer with transparent latches and differential outputs. When the Latch Enable (LEN) is LOW, the latch is transparent, and output data is controlled by the multiplexer select controls. A logic HIGH on LEN latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.

This data sheet provides data for the MC10E/100E256, including pin definitions, function table and logic diagram.

The MC10E/100E241 is an 8-bit shiftable register. Unlike a standard universal shift register such as the E141, the E241 features internal data feedback organized so that the SHIFT control overrides the HOLD/LOAD control. This enables the normal operations of HOLD and LOAD to be toggled with a single control line without the need for external gating. It also enables switching to scan mode with the single SHIFT control line. The eight inputs D0-D7 accept parallel input data, while S-IN accepts serial input data when in shift mode. Data is accepted a setup time before the positive-going edge of CLK; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero.

MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. It features a maximum clock-to-output delay, dual differential outputs, master reset, and scan output.

The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to conserve array output cell functionality and also output pins. The input shift register is designed with control logic which greatly facilitates its use in boundary scan applications.

MC10E/100E211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal (PECL is an acronym for Positive ECL, PECL levels are ECL levels referenced to +5V rather than ground). If a single-ended input is to be used the VBB pin should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB supply is designed to act as the switching reference for the input of the E211 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current.

The MC10E/100E211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal (PECL is an acronym for Positive ECL, PECL levels are ECL levels referenced to +5V rather than ground). If a single-ended input is to be used the VBB pin should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB supply is designed to act as the switching reference for the input of the E211 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current.

The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part–to–part skew down to an output–to–output skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111’s to accomplish the same task. The MC100LVE210 works from a –3.3V supply while the MC100E210 provides identical function and performance from a standard –4.5V 100E voltage supply.

The MC10EL/100EL04 is a 2-input AND/NAND gate with higher performance capabilities. With propagation delays and output transition times significantly faster than the E104 the EL04 is ideally suited for those applications which require the ultimate in AC performance.