Industrial

MC10EL/100EL35 is a high-speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. It features a 525ps propagation delay, 2.2GHz toggle frequency, high bandwidth output transitions, 75kΩ internal input pulldown resistors, and >1000V ESD protection.

The MC10EL/100EL35 is a high speed JK flip-flop with 525ps propagation delay, 2.2GHz toggle frequency, high bandwidth output transitions, 75kΩ internal input pulldown resistors and >1000V ESD protection.

The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications.

The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications

The MC10EL/100EL33 is a 1:4 divider in the MC10EL/100EL series. It features 650ps propagation delay, 4.0GHz toggle frequency, high bandwidth output transitions, 75kΩ internal input pulldown resistors, and >1000V ESD protection.

The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. Because the mature MOSAIC 1.5 process is used, low cost can be added to the list of features. The ELT22 is available in both ECL standards: the 10ELT is compatible with positive MECL 10H logic levels while the 100ELT is compatible with positive ECL 100K logic levels.

This document is about the technical data of MC10ELT/100ELT21

The MC10ELT/100ELT21 is a differential signal converter that is used to convert PECL signals and TTL signals

The MC10ELT/100ELT20 is a TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of the ELT20 makes it ideal for those applications where space, performance and low power are at a premium. Because the mature MOSAIC 1.5 process is used, low cost can be added to the list of features. The ELT20 is available in both ECL standards: the 10ELT is compatible with positive MECL 10H logic levels while the 100ELT is compatible with positive ECL 100K logic levels.

The MC100LVEL/EL91 is a triple PECL to ECL translator. It receives low voltage PECL signals and translates them to differential ECL output signals. The MC100EL91 receives standard voltage PECL signals and translates them to differential ECL output signals. Supports low voltage operation with 620ps typical propagation delays. Supports standard voltage operation with 670ps typical propagation delays. Fully differential design. 20-lead SOIC packaging.

The MC100LVEL/EL91 is a triple PECL to ECL translator. The MC100LVEL91 receives low voltage PECL signals and translates them to differential ECL output signals. The MC100EL91 receives standard voltage PECL signals and translates them to differential ECL output signals. It has features such as low voltage operation, typical propagation delays of 620ps for MC100LVEL91 and 670ps for MC100EL91, fully differential design, and 20-lead SOIC packaging. It also has a VBB output for interfacing with single-ended PECL signals and requires three power rails for level translation. The D input is biased in open input conditions.

The MC100LVEL/EL90 is a triple ECL to PECL translator. The device receives either standard or low voltage differential ECL signals and translates them to either standard or low voltage differential PECL output signals. The LVEL device can handle the low voltage signals while the EL device is designed for the standard signals. It is possible to have low voltage signals on one side and standard signals on the other if the LVEL90 is used.

The MC100LVEL/EL90 is a triple ECL to PECL translator that receives standard or low voltage differential ECL signals and translates them to standard or low voltage differential PECL output signals.