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The DS90CF581 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 40 MHz, 24 bits of RGB data and 4 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY, CNTL) are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data throughput is 140 Megabytes per second. This transmitter is intended to interface to any of the FPD Link receivers. The chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display (FPD) Link— 65 MHz. The product converts 21 bits of CMOS/TTL data into three LVDS data streams and parallel transmits a phase-locked transmit clock and data streams over a fourth LVDS link. At a transmit clock frequency of 65 MHz, 21 bits of input data are sampled and transmitted every cycle of the transmit clock. With a 65 MHz clock, the data throughput is 171 MB/s. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
DS90LT012AH is a low power LVDS receiver launched by Nexperia, supporting a working temperature range of -40 to 125 ℃ and a maximum working frequency of 400 Mbps.
The DS90CF383 is a +3.3V LVDS transmitter from National Semiconductor Corporation that supports a 24-bit Flat Panel Display (FPD) Link, and uses a 65 MHz transmit clock to sample 28 bits of input data per cycle and transmit it at a rate of 455 Mbps per LVDS data channel.
DS90CF386/DS90CF366 is a LVDS receiver chip produced by TI company. It can convert four LVDS data streams (up to 2.38 Gbps throughput or 297.5 megabytes/second bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL)
The DS90CF383B is a programmable LVDS transmitter that converts 28 bits of CMOS/TTL data into four LVDS data streams. It supports a transmit clock frequency of 65 MHz and can transmit 24 bits of RGB data and 3 bits of LCD timing and control data at a rate of 455 Mbps per LVDS data channel. The DS90CF383B is fixed as a Falling edge strobe transmitter and will interoperate with a Falling edge strobe Receiver (DS90CF386) without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
The DS90CF363 is a 3.3V LVDS transmitter, 18-bit Flat Panel Display (FPD) link - 65 MHz. It converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 170 Mbytes/sec. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
DS90C402 is a dual low voltage differential signaling (LVDS) receiver from National Semiconductor Corporation. It features ultra low power dissipation and can operate at data rates up to 155.5 Mbps.
The DS90C401 is a dual driver device optimized for high data rate and low power applications. This device along with the DS90C402 provides a pair chip solution for a dual high speed point-to-point interface. The DS90C401 is a current mode driver allowing power dissipation to remain low even at high frequency. In addition, the short circuit fault current is also minimized. The device is in a 8 lead small outline package. The differential driver outputs provides low EMI with its low output swings typically 340 mV.
DS90CF383B is a +3.3V programmable LVDS transmitter from ST. It supports 24-bit FPD link and transmit frequency up to 65MHz. This device uses falling edge trigger, and can be used with DS90CF386 (falling edge trigger receiver) to solve the EMI and cable size problems associated with wide, high speed TTL interfaces.
The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 784Mbps, providing a total throughput of 5.7Gbps (714 Megabytes per second). The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive. To increase bandwidth, the maximum pixel clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. The DS90C387A transmitter provides a second LVDS output clock. Both LVDS clocks are identical. This feature supports backward compatibility with the previous generation of FPD-Link Receivers - the second clock allows the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit FPD-Link receivers. This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications.
