MAXIM Manuals

The MAX1123 is a monolithic 10-bit, 210Msps analog-to-digital converter (ADC) optimized for outstanding dynamic performance at high IF frequencies up to 500MHz. The product operates with conversion rates of up to 210Msps while consuming only 460mW. At 210Msps and an input frequency of 100MHz, the MAX1123 achieves a spurious-free dynamic range (SFDR) of 74.5dBc. Its excellent signal-to-noise ratio (SNR) of 57.4dB at 10MHz remains flat (within 1.5dB) for input tones up to 500MHz. This makes the MAX1123 ideal for wideband applications such as digital predistortion in cellular base-station transceiver systems. The MAX1123 requires a single 1.8V supply. The analog input is designed for either differential or single- ended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 420MHz. This helps to reduce the phase noise of the input clock source. A differential LVDS sampling clock is recommended for best performance. The converter’s digital outputs are LVDS compatible, and the data format can be selected to be either two’s complement or offset binary. The MAX1123 is available in a 68-pin QFN with exposed pad (EP) and is specified over the industrial (-40°C to +85°C) temperature range. For pin-compatible, lower and higher speed versions of the MAX1123, refer to the MAX1122 (170Msps) and the MAX1124 (250Msps) data sheets. For a higher speed version, refer to the MAX1125 (350Msps) data sheet.

MAX1121 is an 8-bit, 250Msps analog-to-digital converter (ADC) optimized for outstanding dynamic performance at high IF frequencies up to 500MHz.

The MAX1127 is a quad, 12-bit analog-to-digital converter (ADC) with fully differential inputs, a pipelined architecture, and digital error correction. This ADC is optimized for low-power, high-dynamic performance for medical imaging, communications, and instrumentation applications. It operates from a 1.7V to 1.9V single supply and consumes only 563mW while delivering a 69.6dB signal-to-noise ratio (SNR) at a 19.3MHz input frequency. In addition to low operating power, it features a 675µA power-down mode for idle periods. An internal 1.24V precision bandgap reference sets the ADC’s full-scale range. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range. A single-ended clock controls the conversion process. An internal duty-cycle equalizer allows for wide variations in input-clock duty cycle. An on-chip phase-locked loop (PLL) generates the high-speed serial low-voltage differential signaling (LVDS) clock. The MAX1127 provides serial LVDS outputs for data, clock, and frame alignment signals. The output data is presented in two’s complement or binary format. Refer to the MAX1126 data sheet for a pin-compatible 40Msps version of the MAX1127. It is available in a small, 10mm x 10mm x 0.9mm, 68-pin QFN package with exposed paddle and is specified for the extended industrial (-40°C to +85°C) temperature range.

The MAX1206 is a 3.3V, 12-bit analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input, driving the internal quantizer. The MAX1206 is optimized for low power, small size, and high dynamic performance. This ADC operates from a single 3.0V to 3.6V supply, consuming only 159mW, while delivering a typical signal-to-noise ratio (SNR) performance of 68.6dB at a 20MHz input frequency. The T/H-driven input stage accepts single-ended or differential inputs. In addition to low operating power, the MAX1206 features a 0.15mW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX1206 to use its internal precision bandgap reference or accept an externally applied reference. A common-mode reference is provided to simplify design and reduce external component count in differential analog input circuits. The MAX1206 supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC's internal duty-cycle equalizer. The MAX1206 features parallel, CMOS-compatible outputs. The digital output format is pin selectable to be either two's complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate power input for the digital outputs accepts a voltage from 1.7V to 3.6V for flexible interfacing with various logic levels.

The MAX1207 is a 3.3V, 12-bit analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input, driving the internal quantizer. The MAX1207 is optimized for low power, small size, and high dynamic performance. This ADC operates from a single 3.0V to 3.6V supply, consuming only 316mW, while delivering a typical signal-to-noise ratio (SNR) performance of 68.5dB at a 32.5MHz input frequency. The T/H-driven input stage accepts single-ended or differential inputs. In addition to low operating power, the MAX1207 features a 0.15mW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX1207 to use its internal precision bandgap reference or accept an externally applied reference. A common-mode reference is provided to simplify design and reduce external component count in differential analog input circuits. The MAX1207 supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer. The MAX1207 features parallel, CMOS-compatible outputs. The digital output format is pin selectable to be either two’s complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate power input for the digital outputs accepts a voltage from 1.7V to 3.6V for flexible interfacing with various logic levels.

The MAX1213 is a monolithic, 12-bit, 170Msps analog-to-digital converter (ADC) optimized for outstanding dynamic performance at high-IF frequencies up to 300MHz. The product operates with conversion rates up to 170Msps while consuming only 788mW. At 170Msps and an input frequency up to 250MHz, the MAX1213 achieves a spurious-free dynamic range (SFDR) of 72.9dBc. Its excellent signal-to-noise ratio (SNR) of 66.2dB at 10MHz remains flat (within 2dB) for input tones up to 250MHz. This ADC yields an excellent low-noise floor of -68dBFS, which makes it ideal for wideband applications such as cable head-end receivers and power-amplifier predistortion in cellular base-station transceivers. The MAX1213 requires a single 1.8V supply. The analog input is designed for either differential or single-ended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 340MHz. This helps to reduce the phase noise of the input clock source. A low-voltage differential signal (LVDS) sampling clock is recommended for best performance. The converter’s digital outputs are LVDS compatible and the data format can be selected to be either two’s complement or offset binary. The MAX1213 is available in a 68-pin QFN package with exposed paddle (EP) and is specified over the industrial (-40°C to +85°C) temperature range. See the Pin-Compatible Versions table for a complete list of part numbers.

The MAX12553 is a 3.3V, 14-bit, 65Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts single- ended or differential signals. The MAX12553 is optimized for low-power, small size, and high dynamic performance. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX12553 ideal for intermediate- frequency (IF) sampling applications. Powered from a single 3.15V to 3.60V supply, the MAX12553 consumes only 363mW while delivering a typical signal-to-noise (SNR) performance of 71dB at an input frequency of 175MHz. In addition to low oper- ating power, the MAX12553 features a 150µW power- down mode to conserve power during idle periods. A flexible reference structure allows the MAX12553 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.10V. The MAX12553 provides a com- mon-mode reference to simplify design and reduce exter- nal component count in differential analog input circuits. The MAX12553 supports both a single-ended and dif- ferential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (DCE). ADC conversion results are available through a 14-bit, parallel, CMOS-com- patible, low-power, high-speed, low-noise output data bus.

The MAX1209 is a 3.3V, 12-bit, 80Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts single-ended or differential signals. The MAX1209 is optimized for low power, small size, and high dynamic performance. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX1209 ideal for intermediate-frequency (IF) sampling applications. Powered from a single 3.0V to 3.6V supply, the MAX1209 consumes only 366mW while delivering a typical signal-to-noise (SNR) performance of 66.5dB at an input frequency of 175MHz. In addition to low operating power, the MAX1209 features a 3µW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX1209 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.15V. The MAX1209 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX1209 supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (DCE). ADC conversion results are available through a 12-bit, parallel, CMOS-compatible output interface.

The MAX1208 is a 3.3V, 12-bit, 80Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts single-ended or differential signals. The MAX1208 is optimized for low power, small size, and high dynamic performance in baseband applications. Powered from a single 3.0V to 3.6V supply, the MAX1208 consumes only 373mW while delivering a typical signal-to-noise (SNR) performance of 68.2dB at an input frequency of 32.5MHz. In addition to low operating power, the MAX1208 features a 3µW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX1208 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.15V. The MAX1208 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX1208 supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (DCE). ADC conversion results are available through a 12-bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two’s complement or Gray code. A data-valid indicator eliminates external components that are normally required to indicate when the ADC is in conversion mode.

The MAX12555 is a 3.3V, 14-bit, 95Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts single- ended or differential signals. The MAX12555 is optimized for high dynamic performance, low power, and small size. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX12555 ideal for intermediate- frequency (IF) sampling applications. Powered from a single 3.3V supply, the MAX12555 con- sumes only 497mW while delivering a typical 72dB sig- nal-to-noise ratio (SNR) performance at a 175MHz input frequency. In addition to low operating power, the MAX12555 features a 300µW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX12555 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.10V. The MAX12555 provides a com- mon-mode reference to simplify design and reduce exter- nal component count in differential analog input circuits. The MAX12555 supports either a single-ended or differ- ential input clock. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty- cycle equalizer (DCE). ADC conversion results are available through a 14-bit, parallel, CMOS-compatible output b

The MAX12554 is a 3.3V, 14-bit, 80Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The MAX12554 is optimized for high dynamic performance, low power, and small size. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX12554 ideal for intermediate-frequency (IF) sampling applications. Powered from a single 3.3V supply, the MAX12554 consumes only 429mW while delivering a typical 70.9dB signal-to-noise ratio (SNR) performance at a 175MHz input frequency. In addition to low operating power, the MAX12554 features a 300µW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX12554 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.10V. The MAX12554 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX12554 supports either a single-ended or differential input clock. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (DCE). ADC conversion results are available through a 14-bit, parallel, CMOS-compatible out

The MAX19538 is a 3.3V, 12-bit, 95Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input accepts single-ended or differential signals. The MAX19538 is optimized for low power, small size, and high dynamic performance. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX19538 ideal for intermediate frequency (IF) sampling applications. Powered from a single 3.3V supply, the MAX19538 consumes only 492mW while delivering a typical 68.4dB signal-to-noise ratio (SNR) performance at a 175MHz input frequency. In addition to low operating power, the MAX19538 features a 63µW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX19538 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.10V. The MAX19538 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX19538 supports either a single-ended or differential input clock drive. The internal clock duty-cycle equalizer accepts a wide range of clock duty cycles. Analog-to-digital conversion results are available through a 12-bit, parallel, CMOS-compatible output bus.

The MAX12527 is a low-power, small-size, 12-bit ADC from MAXIM that features fully differential wideband track-and-hold (T/H) inputs, driving internal quantizers. The MAX12527 is optimized for low power, small size, and high dynamic performance in intermediate frequency (IF) and baseband sampling applications. This dual ADC operates from a single 3.3V supply, consuming only 620mW while delivering a typical 69.8dB signal-to-noise ratio (SNR) performance at a 175MHz input frequency. The T/H input stages accept single-ended or differential inputs up to 400MHz. In addition to low operating power, the MAX12527 features a 166µW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX12527 to use the internal 2.048V bandgap reference or accept an externally applied reference and allows the reference to be shared between the two ADCs. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.15V. The MAX12527 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX12527 supports either a single-ended or differential input clock. User-selectable divide-by-two (DIV2) and divide-by-four (DIV4) modes allow for design flexibility and help eliminate the negative effects of clock jitter. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (DCE).

The MAX12557 is a dual 3.3V, 14-bit analog-to-digital converter (ADC) featuring fully differential wideband track-and-hold (T/H) inputs, driving internal quantizers. The MAX12557 is optimized for low power, small size, and high dynamic performance in intermediate frequency (IF) and baseband sampling applications. This dual ADC operates from a single 3.3V supply, consuming only 610mW while delivering a typical 72.5dB signal-to-noise ratio (SNR) performance at a 175MHz input frequency. The T/H input stages accept single-ended or differential inputs up to 400MHz. In addition to low operating power, the MAX12557 features a 166µW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX12557 to use the internal 2.048V bandgap reference or accept an externally applied reference and allows the reference to be shared between the two ADCs. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.15V. The MAX12557 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX12557 supports either a single-ended or differential input clock. User-selectable divide-by-two (DIV2) and divide-by-four (DIV4) modes allow for design flexibility and help eliminate the negative effects of clock jitter. Wide variations in the clock duty cycle are compensated with the ADCs internal duty-cycle equalizer (DCE).