TEXAS Manuals

The CDC509 is a high-performance, low-jitter, low-skew phase-lock loop (PLL) clock driver from Cypress Semiconductor. It uses a PLL to precisely align the feedback (FBOUT) output to the clock (CLK) input signal, both in frequency and phase. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3 V VCC and is designed to drive up to five clock loads per output. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC509 does not require external RC networks. The PLL's loop filter is integrated on-chip, reducing PCB area.

The CDC392 is a 1-to-6 line clock driver with selectable polarity and 3-state outputs. It is designed for clock distribution and clock generation applications, providing low output skew. The inputs are TTL-compatible and the outputs are CMOS-compatible. Various combinations of true and complementary outputs can be obtained using the polarity control inputs. The distributed VCC and GND pins help reduce switching noise. The outputs have high drive capability (-32mA IOH, 32mA IOL). The CDC392 is built using state-of-the-art EPIC-ΙΙB BiCMOS design, which significantly reduces power dissipation. It is packaged in a plastic small-outline package.

The CDC351 is a high-performance clock driver circuit from Texas Instruments that distributes one input clock signal to 10 output clock signals with minimum skew. The CDC351 operates at 3.3 V VCC, and has high drive current and low power consumption.

The CDC341 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a low state regardless of the A input. The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND. The CDC341 is characterized for operation from 0°C to 70°C.

The CDC340 is a high-performance clock driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a high state regardless of the A input. The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND. The CDC340 is characterized for operation from 0°C to 70°C.

The CDC339 is a high-performance, low-skew clock driver specifically designed for applications requiring synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. It features low output skew and low pulse skew, TTL-compatible inputs and outputs, distributes one clock input to eight outputs (four same-frequency outputs and four half-frequency outputs), distributed VCC and ground pins to reduce switching noise, high-drive outputs, state-of-the-art EPIC-IIIB BiCMOS design to reduce power dissipation, and multiple package options.

cdc337 is a single clock input, eight-way clock output clock driver with low output skew and low pulse skew launched by texas instruments, which can simultaneously output clock frequency and one-half of the clock frequency.

The CDC330 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring output signals at both the primary clock frequency and one-half the primary clock frequency. This device contains two banks that fan out one input to three same-frequency outputs and one bank that fans out one input to four half-frequency outputs with minimum skew for clock distribution. Each bank of Y outputs switch in phase and at the same frequency as its clock (A) input. The four Q outputs switch at one-half the frequency of their clock (2A) input. When the output-enable (2OE) input is low and the preset (PRE) input is high, the Q outputs toggle on high-to-low transitions of 2A. Taking PRE low asynchronously presets the Q outputs to...

CDC303 is an eight-bit divide-by-two circuit/clock driver from TI. The device has low output skew and pulse skew, with a maximum output skew of 1ns and a maximum pulse skew of 1ns. CDC303's inputs and outputs are TTL-compatible. The device is available in plastic small-outline (D) package and standard plastic (N) 300mil DIP packages.

The CDC304 is a circuit with 8 flip-flops designed to have low skew between outputs. It has a maximum output skew of 1ns and maximum pulse skew of 1.5ns. The product features TTL-compatible inputs and outputs, and utilizes center-pin VCC and GND configurations to minimize high-speed switching noise. It is suitable for clock drivers where a divide-by-two function is required.

CDC305 is a clock driver produced by TI company. This clock driver has TTL-compatible inputs and outputs, low skew between outputs, and eight outputs, four of which are synchronized with the CLK signal and four of which are out of phase with the CLK signal.

The CDC318 is a high-performance clock buffer that distributes one input (A) to 18 outputs (Y) with minimum skew for clock distribution. The CDC318 operates from a 3.3-V power supply, and is characterized for operation from 0°C to 70°C. The device provides a standard mode (100K-bits/s) I2C serial interface for device control. The implementation is as a slave/receiver. The device address is specified in the I2C device address table. Both of the I2C inputs (SDATA and SCLOCK) provide integrated pullup resistors (typically 140 kΩ) and are 5-V tolerant. Three 8-bit I2C registers provide individual enable control for each of the outputs. All outputs default to enabled at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit is written to the control register.

cdc318a is a clock buffer produced by texas instruments. it supports 100mhz clock frequency and can output 18 clock signals at the same time.

CDC319 is a 1-to-10 clock buffer that supports SDRAM clock buffering applications. The output skew (tsk(o)) is less than 250 ps, and the pulse skew (tsk(p)) is less than 500 ps. It supports up to two unbuffered SDRAM DIMMs (Dual Inline Memory Modules). The I2C serial interface provides individual enable control for each output. It operates at 3.3V. Distributed VCC and ground pins reduce switching noise. The ESD protection voltage exceeds 2000V, meeting the requirements of MIL-STD-883 Method 3015. It is packaged in a 28-pin Shrink Small Outline (DB) package.