TEXAS Manuals

The CDC208 is a dual 1-line to 4-line clock driver designed for clock distribution applications. It features low-skew propagation delay, TTL-compatible inputs, CMOS-compatible outputs, flow-through architecture for optimized PCB layout, center-pin VCC and GND pin configurations to minimize high-speed switching noise, and is manufactured using the EPIC (Enhanced-Performance Implanted CMOS) 1-µm process. The device also offers output-enable inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the input signal.

CDC208 is a clock driver produced by TI company, it can distribute one input signal to four output terminals with minimum jitter and high reliability.

cdc2351 is a clock driver circuit from dallas semiconductor that distributes one input (a) to ten outputs (y) with minimum skew for clock distribution. the output-enable (oe) input disables the outputs to a high-impedance state. each output has an internal series damping resistor to improve signal integrity at the load. the cdc2351 operates at nominal 3.3-v vcc.

The CDC2509 is a 3.3V phase-lock loop clock driver that uses a PLL to precisely align the feedback output to the clock input signal in both frequency and phase. This product is specifically designed for use with synchronous DRAM. The CDC2509 operates at 3.3V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control inputs (1G and 2G). When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2509 does not require an external RC network.

The CDC2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2509A operates at 3.3-V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products...

cdc2509b 3.3-v phase-lock loop clock driver is a phase-lock loop clock distributor for synchronous dram applications. it distributes one clock input to one bank of five and one bank of four outputs. each output bank has a separate output enable. the external feedback (fbin) terminal is used to synchronize the outputs to the clock input. cdc2509b operates at 3.3-v vcc. it also provides integrated series damping resistors, making it ideal for driving point-to-point loads.

The document describes the features and characteristics of the CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER, including low-output skew, differential low-voltage pseudo-ECL (LVPECL)-compatible inputs and outputs, output reference voltage, and single-ended LVPECL-compatible output enable.

The MPC506A/MPC507A are 16-channel single-ended analog multiplexers and 8-channel differential analog multiplexers produced by Texas Instruments.

MSC1200 is a high-precision analog-to-digital converter (ADC) and digital-to-analog converter (DAC) with 8051 microcontroller and flash memory produced by TI.

The SN74CBT3306 is a dual FET bus switch device manufactured by Texas Instruments. It features independent line switches. Each switch is disabled when the associated output-enable (OE) input is high. The SN74CBT3306 is characterized for operation from -40°C to 85°C.

This data sheet describes the SN74CBT3125 quadruple FET bus switch

This document is a technical manual for LM339 and LM331 low voltage comparators. It mainly introduces the performance characteristics of the product, including the supply voltage range, input voltage range, output voltage range, and output current range. In addition, it provides the product packaging, model, ordering information, etc.

LMV331 is a single-supply low-voltage comparator with a supply voltage of 2.7V to 5.5V. It offers low power consumption, high performance, high reliability and ultra-small package. It is widely used in the low-voltage circuit design of portable consumer products.

The LMV321, LMV358, and LMV324/LMV324S are single, dual, and quad low-voltage (2.7 V to 5.5 V) operational amplifiers with rail-to-rail output swing. The LMV324S is a variation of the standard LMV324 that includes a power-saving shutdown feature that reduces supply current to a maximum of 5 µA per channel when the amplifiers are not needed. The LMV321, LMV358, LMV324, and LMV324S are the most cost-effective solutions for applications where low-voltage operation, space saving, and low price are needed. These amplifiers were designed specifically for low-voltage (2.7 V to 5 V) operation, with performance specifications meeting or exceeding the venerable LM358 and LM324 devices that operate from 5 V to 30 V. Additional features of the LMV3xx devices are a common-mode input voltage range that includes ground, 1-MHz unity-gain bandwidth, and 1-V/µs slew rate.

The NE5534 and NE5534A are high-performance operational amplifiers combining excellent dc and ac characteristics. Some of the features include very low noise, high output-drive capability, high unity-gain and maximum-output-swing bandwidths, low distortion, and high slew rate. These operational amplifiers are compensated internally for a gain equal to or greater than three. Optimization of the frequency response for various applications can be obtained by use of an external compensation capacitor between COMP and COMP/BAL. The devices feature input-protection diodes, output short-circuit protection, and offset-voltage nulling capability with use of the BALANCE and COMP/BAL pins (see the application circuit diagram). For the NE5534A, a maximum limit is specified for the equivalent input noise voltage.