TEXAS Manuals

cdc328 is a clock driver produced by Texas Instruments. It can distribute one input signal to six output ports, with low output skew and optional positive and negative polarity. It is mainly used for clock distribution and clock generation applications.

CDC328A 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY is a clock driver that provides 1 input and 6 outputs, with polarity control.

CDC329 is a clock driver product from Texas Instruments. It can distribute one input clock signal to six output ports and provide low switching noise, high drive output and other features.

CDC2510C is a 3.3V low-skew, low-jitter, phase-lock loop (PLL) clock driver released by TI. It uses a PLL to precisely align the feedback output (FBOUT) with the clock input (CLK) signal in both frequency and phase. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC = 3.3 V. It also provides integrated series damping resistors, making it ideal for driving point-to-point loads. One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. All outputs can be enabled or disabled through a single output enable input. When the G input is high, all outputs are enabled.

The CDC2516 3.3-V Phase-Lock Loop Clock Driver is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2516 operates at 3.3-V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. Four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the 1G, 2G, 3G, and 4G control inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2516 does not require external RC network.

The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC2536 operates at 3.3-V VCC and is designed to drive a 50-Ω transmission line. The CDC2536 also provides on-chip series-damping resistors, eliminating the need for external RC network.

The CDC2582 is a high-performance, low-skew, low-jitter clock driver that uses a phase-lock loop (PLL) to precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN, CLKIN) input.

The CDC2586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input signals.

The CDC2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2510 operates at 3.3-V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2510 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing

the cdc2509c is a 3.3v phase-lock loop clock driver from ti. the device supports frequencies from 25mhz to 125mhz and offers low distortion and jitter.

cdc203 is a 3.3v six-way switching circuit produced by texas instruments. It is suitable for applications requiring low skew between switching outputs. cdc203 adopts flow-through architecture, optimizes pcb layout, center-pin vcc and gnd pin configuration can minimize high-speed switching noise. The device is manufactured using 1-μm epic (enhanced performance implanted cmos) process, has a typical latch-up immunity of 500ma at 125℃, and is packaged in plastic small-outline package.

The CDC204 is a device that contains six independent inverters, designed for applications requiring low skew between switching outputs. It has CMOS-compatible inputs and outputs, with a flow-through architecture that optimizes PCB layout. The device is manufactured using the EPIC (Enhanced-Performance Implanted CMOS) 1-µm process, and has a high latch-up immunity. It is available in various package options.