TEXAS Manuals

The CDC924 is a clock synthesizer/driver for PC motherboards that supports Pentium III class motherboards. It uses a 14.318 MHz crystal input to generate multiple output frequencies. The CDC924 includes spread spectrum clocking (SSC) with 0.5% downspread for reduced electromagnetic interference (EMI) performance. It also features power management control terminals, low output skew and jitter for clock distribution, and supports 2.5 V and 3.3 V supplies. The CDC924 generates various clocks including CPU, PCI, APIC, and REF clock signals.

cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs

CDC921 is a clock synthesizer/driver produced by TI, which supports a single Pentium III class microprocessor and can generate multiple output frequencies. It also has low output skew and jitter and can be used on PC motherboards.

This document describes the features and characteristics of CDCR81 DIRECT RAMBUS CLOCK GENERATOR SCAS606B, including support for Direct Rambus memory subsystem, synchronization with external system or processor clock, three power operating modes, single 3.3V supply, wide frequency range for phase-locked loop input, etc.

CDC857-2 and CDC857-3 are 2.5-/3.3-V phase-lock loop clock drivers for Double Data Rate Synchronous DRAM applications. It distributes one differential clock input to ten differential outputs. External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input. It operates at VCC = 2.5 V and AVCC = 3.3 V. And it is packaged in plastic 48-pin (DGG) thin shrink small-outline package (TSSOP).

the cdc516 is a phase-lock loop clock driver from texas instruments that is specifically designed for use with synchronous drams. it uses a phase-lock loop (pll) to precisely align, in both frequency and phase, the feedback output (fbout) to the clock (clk) input signal. the device operates at 3.3v vcc and is designed to drive up to five clock loads per output. four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. each bank of outputs can be enabled or disabled separately via the 1g, 2g, 3g, and 4g control inputs. when the g inputs are high, the outputs switch in phase and frequency with clk; when the g inputs are low, the outputs are disabled to the logic-low state. unlike many products containing plls, the cdc516 does not require external rc networks. the loop filter for the pll is included on-chip, minimizing the number of external components required and improving product reliability.

The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V VCC and is designed to drive a 50-Ω transmission line. The feedback input (FBIN) is used to synchronize the output clocks.

cdc5801 is a low jitter clock multiplier and divider with programmable delay and phase alignment, supporting x4, x6, x8 multiplication, supporting input frequency from 19mhz to 125mhz, output frequency from 150mhz to 500mhz.

The CDC5806 is a clock generator for digital TV applications. It synthesizes video clocks, audio clocks, CPU clock, ASIC clock, USB clock, and memory card clock from a 54-MHz system clock. It utilizes three phase-locked loops (PLLs) to generate different frequencies, and it features high performance, low jitter, and low peak-to-peak clock jitter.

The CDC582 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN, CLKIN) input signals. It is specifically designed to operate at speeds from 50 MHz to 100 MHz or lower.

The CDC586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN).