TEXAS Manuals

This file is the scas727b manual for the cdcp1803 clock driver

The product is a clock buffer that supports 1:3 LVPECL clock output and programmable divider. It features low output skew, wide common mode range, differential input stage and single-ended input signal VBB bias voltage output.

The CDCM1802 is a clock buffer with a programmable divider, LVPECL I/O and additional LVCMOS output. It distributes one differential clock input to one LVPECL differential clock output and one LVCMOS single-ended output. The programmable output divider is suitable for LVPECL and LVCMOS outputs. The 1.6-ns output skew between LVCMOS and LVPECL transitions minimizes noise. The device operates at a supply voltage of 3.3 V (2.5 V functional) and has a signaling rate of up to 800 MHz LVPECL and 200 MHz LVCMOS. The differential input stage has a wide common-mode range and also provides a VBB bias voltage output for single-ended input signals. The receiver input threshold is ±75 mV. The device is packaged in a 16-pin QFN package (3 mm x 3 mm).

The CDCLVP110 is a low-voltage 1:10 LVPECL/HSTL with selectable input clock driver. It distributes one differential clock input pair (CLK0, CLK1) to ten pairs of differential LVPECL clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources to an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines. If single-ended input operation is required, the VBB reference voltage output is used. In this case, the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

The CDCLVD110 is a programmable low-voltage 1:10 LVDS clock driver. It features low-output skew, distribution of one pair of differential clock inputs to 10 pairs of differential clock outputs, VCC range of 2.5V, and a typical signaling rate capability of up to 1.1 GHz.

CDCFR83 is a Direct Rambus clock generator from Texas Instruments that provides a 533 MHz clock source for Direct Rambus memory systems for an 1066 MHz data transfer rate. CDCFR83 can also synchronize the Rambus channel clock domain with an external system clock or processor clock. CDCFR83 employs three power operating modes to minimize power consumption for mobile applications and other power-sensitive applications. CDCFR83 is powered by a single 3.3 V supply and consumes 120 mW (typical) and is packaged in a Shrink Small-Outline Package (DBQ). CDCFR83 supports frequency multipliers of 4, 6, 8, 16/3, does not require external components for PLL, supports independent channel clocking, and has spread spectrum clocking tracking capability to reduce EMI. CDCFR83 is designed for use with TI's 133 MHz clock synthesizers CDC924 and CDC921. Its cycle-to-cycle jitter is less than 40 ps at 533 MHz. CDCFR83 has been certified by Gigatest Labs to exceed the Rambus DRCG validation requirement and supports an industrial temperature range of -40°C to 85°C.

the cdcf5801 is a low-jitter clock multiplier that can multiply the input clock frequency by 1, 2, 4, or 8 times. The output frequency range is 25 mhz to 280 mhz, and the input frequency range is 12.5 mhz to 240 mhz. It has single-ended input and differential output, and can drive lvpecl, lvds, and lvttl.

The CDCF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCF2509 operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control.

The CDC9843 is a high-performance clock synthesizer/driver that generates the system clocks necessary to support Pentium®/82430HX/82430VX and PentiumPro 82440FX chipsets. Four host-clock outputs (HCLKn) are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control inputs. Six PCI-clock outputs (PCLKn) are half the frequency of CPU clock outputs and are delayed 1 ns to 4 ns from the rising edge of the CPU clock. In addition, a universal serial bus (USB) clock output at 48 MHz (SBCLK), a floppy controller clock at 24 MHz (FCCLK), and two 14.318-MHz reference clock outputs (REF0, REF1) are provided. All output frequencies are generated from a 14.318-MHz crystal input.

The CDC9842 is a high-performance clock synthesizer/driver that generates the system clocks necessary to support Pentium/82430X/82430VX and PentiumPro 82440FX chipsets. It provides four host-clock outputs (HCLKn) that are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control inputs. Six PCI-clock outputs (PCLKn) are half the frequency of CPU clock outputs and are delayed 1 ns to 4 ns from the rising edge of the CPU clock. In addition, a universal serial bus (USB) clock output at 48 MHz (SBCLK) and three 14.318-MHz reference clock outputs (REF0, REF1, REF2) are provided. All output frequencies are generated from a 14.318-MHZ crystal input. A reference clock can be provided at the X1 input instead of the crystal input.

cdc9841 pc motherboard clock synthesizer/driver with 3-state outputs

The CDC960 is a clock synthesizer/driver and buffer that generates CPU, PCI, PCI/LDT, USB, FDC, and REF system clock signals to support PCs with an AMD-K8 Clawhammer-class system. All output frequencies are generated from a 14.318-MHz crystal input.

This document is about CDC950 clock synthesizer/driver, which can generate 8 host clock (100/133 MHz) clocks, 1 CLK33 clock (3.3V, 33.3MHz), 1 REFCLK clock (3.3V, 14.318MHz) and 2 3V48 clocks (3.3V, 180° shifted pairs, 48MHz)

cdc930 133-mhz differential clock synthesizer/driver for pc motherboards with 3-state outputs