Xilinx ISE FPGA/CPLD Design Tool User Manual

About this manual

This manual introduces the Xilinx ISE design environment, covering the complete design flow from project creation, HDL editing, synthesis, implementation, to simulation and programming. It explains the purpose of each tool module such as Project Navigator, HDL Editor, StateCAD, and the integrated ModelSim simulator.

The document also details device support, including Spartan‑3, Virtex‑II Pro, CoolRunner CPLD families, and provides step‑by‑step instructions for timing analysis, floorplanning, and generating post‑map simulation models. This manual is written in Chinese.

What's inside

• 1.1 FPGA/CPLD Overview
• 2.1 Project Navigator
• 2.2 HDL Editor
• 3.1 ModelSim Simulation
• 4.1 Synplify / Synplify Pro
• 5.4 Constraints Editor
• 6.1 Timing Analyzer
• 7.1 XPower Power Estimation
• 9.2 I2C Interface Design

Specifications

Frequently asked questions

Which simulation tool is integrated with Xilinx ISE?

Xilinx ISE integrates the ModelSim simulator for functional verification and post‑map simulation.