Technical data sheet for the Philips 74HC/HCT192 presettable synchronous BCD decade up/down counter.
The 74HC/HCT192 is a high‑speed Si‑gate CMOS device that provides synchronous reversible counting with separate up (CP U) and down (CP D) clock inputs. It supports asynchronous parallel load (PL) and master reset (MR) functions, and its outputs change state on the low‑to‑high transition of the selected clock input. The device is pin‑compatible with low‑power Schottky TTL and conforms to JEDEC standard no. 7A.
The data sheet includes features, pin descriptions, functional tables, DC and AC characteristics, and typical timing diagrams. It also provides quick reference data such as supply voltage, propagation delays, maximum clock frequency, and load capacitance for both HC and HCT versions.
| Maximum clock frequency (fmax) | 40 MHz (HC) / 45 MHz (HCT) |
|---|---|
| Output load capacitance (CL) | 15 pF |
The count‑up clock input is CP U and the count‑down clock input is CP D.
TCU (terminal count up) and TCD (terminal count down) are active‑low outputs that indicate when the counter reaches the maximum (9) or zero count, respectively.