Technical specification and data sheet for the Micron MT45W1MW16BDGB 16Mb Async/Page/Burst CellularRAM 1.0 memory device.
This document provides technical specifications and operational details for the Micron MT45W1MW16BDGB, a high-speed CMOS PSRAM memory device organized as 1 Meg x 16 bits. Designed for low-power portable applications, it features an industry-standard burst mode Flash interface that increases read/write bandwidth compared to other SRAM or Pseudo SRAM offerings.
The datasheet details the device's functional blocks, including a DRAM memory array and two user-accessible control registers: the Bus Configuration Register (BCR) for system bus interaction and the Refresh Configuration Register (RCR) for controlling refresh operations. Key features include asynchronous, page, and burst modes, as well as low-power mechanisms such as Partial-array refresh (PAR), Temperature-compensated refresh (TCR), and Deep power-down (DPD).
| Capacity | 16Mb (1 Meg x 16 bits) |
|---|---|
| Random access time | 70ns |
| VCC Voltage Range | -1.7–3.6V |
| Intrapage read access time | 20ns |
| Maximum clock rate | 104 MHz |
| Burst initial latency | 39 ns |
| Package Type | 54-ball VFBGA |
The device supports asynchronous, page, and burst operations.
Yes, it includes Temperature-compensated refresh (TCR), Partial-array refresh (PAR), and Deep power-down (DPD) mode.
The maximum clock rate is 104 MHz.